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1 superpipelined architecture
вчт суперконвейерная архитектураEnglish-Russian electronics dictionary > superpipelined architecture
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2 superpipelined architecture
вчт. суперконвейерная архитектураThe New English-Russian Dictionary of Radio-electronics > superpipelined architecture
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3 architecture
1) структура; конфигурация; конструкция2) вчт архитектура•- bit-addressable architecture
- bit-slice architecture
- boundary scan architecture - bus architecture
- bus structured architecture
- chip architecture
- client-server architecture
- closed architecture - computer family architecture
- connectionist architecture
- data bus architecture
- data flow architecture
- defense-in-depth security architecture
- die architecture
- digital network architecture - dynamic power management architecture
- dynamic scalable architecture
- engagement architecture - firmware architecture
- hardware architecture
- Harvard architecture
- high-performance computer architecture
- hub architecture
- industry standard architecture
- linear addressing architecture
- machine check architecture
- medium control architecture
- micro channel architecture
- MIMD architecture
- MISD architecture
- modular architecture
- multi-issue architecture
- multiple-instruction multiple-data architecture
- multiple-instruction single-data architecture
- multiprocessor architecture
- multi-tier architecture
- network architecture
- neural network architecture - pipelined architecture
- Princeton architecture
- problem-oriented architecture
- process architecture
- PS/2 architecture - security architecture
- segmented addressing architecture
- segmented memory architecture
- serial storage architecture
- shading architecture
- shared memory architecture - single-instruction multiple-data architecture
- single-instruction single-data architecture
- SISD architecture
- slice architecture
- software architecture
- stack architecture
- stack-based architecture
- superpipelined architecture - systolic array architecture - tree architecture
- tree-and-branch architecture - unified memory architecture
- very long instruction word architecture
- virtual architecture - von Neumann architecture -
4 architecture
1) структура; конфигурация; конструкция2) вчт. архитектура•- bit-addressable architecture
- bit-slice architecture
- boundary scan architecture
- broadband network architecture
- bubble chip architecture
- bus architecture
- bus structured architecture
- chip architecture
- client-server architecture
- closed architecture
- common object request brokers architecture
- computer architecture
- computer family architecture
- connectionist architecture
- data bus architecture
- data flow architecture
- defense-in-depth security architecture
- die architecture
- digital network architecture
- distributed enterprise management architecture
- document content architecture
- document interchange architecture
- domain architecture
- dynamic power management architecture
- dynamic scalable architecture
- engagement architecture
- enhanced industry standard architecture
- extensible architecture
- final-form-text document content architecture
- firewall architecture
- firmware architecture
- hardware architecture
- Harvard architecture
- high-performance computer architecture
- hub architecture
- industry standard architecture
- linear addressing architecture
- machine check architecture
- medium control architecture
- micro channel architecture
- MIMD architecture
- MISD architecture
- modular architecture
- multi-issue architecture
- multiple-instruction multiple-data architecture
- multiple-instruction single-data architecture
- multiprocessor architecture
- multi-tier architecture
- network architecture
- neural network architecture
- office document architecture
- office document management architecture
- open architecture
- open document architecture
- open document management architecture
- open network architecture
- organizational architecture
- pipelined architecture
- Princeton architecture
- problem-oriented architecture
- process architecture
- PS/2 architecture
- revisable-form-text document content architecture
- scalable processor architecture
- security architecture
- segmented addressing architecture
- segmented memory architecture
- serial storage architecture
- shading architecture
- shared memory architecture
- signal computing system architecture
- SIMD architecture
- single-instruction multiple-data architecture
- single-instruction single-data architecture
- SISD architecture
- slice architecture
- software architecture
- stack architecture
- stack-based architecture
- superpipelined architecture
- systems application architecture
- systems monitor architecture
- systems network architecture
- systolic architecture
- systolic array architecture
- Texas Instruments graphics architecture
- three-tier architecture
- tree architecture
- tree-and-branch architecture
- twin-bank memory architecture
- two-level cache architecture
- unified memory architecture
- very long instruction word architecture
- virtual architecture
- virtual intelligent storage architecture
- VLIW architecture
- von Neumann architecture
- Windows open services architectureThe New English-Russian Dictionary of Radio-electronics > architecture
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5 суперконвейерная архитектура
Русско-английский словарь по электронике > суперконвейерная архитектура
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6 суперконвейерная архитектура
Русско-английский словарь по радиоэлектронике > суперконвейерная архитектура
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7 pipeline
1) (см. тж. instruction pipeline, processor pipeline) - конвейер"сборочная линия" - цепочка параллельно работающих исполнительных устройств центрального процессора, на которой обработка команд разбивается на ряд небольших шагов, стадий или ступеней, выполняемых за один такт. Конвейер организован таким образом, что выходные данные одного устройства поступают на вход другого. Число стадий называется длиной конвейера. Использование конвейера позволяет начать исполнение следующей машинной команды в одном блоке до завершения предыдущей, т. е. с перекрытием по времени (различные стадии нескольких команд выполняются ЦП параллельно). Какова длина конвейера, столько команд одновременно он и может обрабатывать - и в идеале конвейеризация обеспечивает выигрыш в производительности (по сравнению с неконвейерными ЦП, non-pipelined processor), соответствующий числу ступеней конвейера. В современных процессорах конвейеры имеют длину до 20 стадий (Pentium 4). Однако параллельная обработка команд возможна не всегда, так как в программе часто встречаются команды условных переходов и ситуации, когда для исполнения команды требуется результат предшествующей команды. В таких случаях, чтобы предотвратить перезагрузку конвейера (см. pipeline break), применяются более сложные процессы: упреждающая обработка (предсказание переходов, branch prediction) или изменение порядка исполнения команд (out-of-order execution).The pipeline must be flushed before the CPU can respond to an interrupt. — Конвейер должен быть очищен перед тем как ЦП сможет реагировать на прерывание см. тж. balanced pipeline, branch delay slot, control-flow pipeline, execute phase, graphics pipeline, instruction pipeline, load delay slot, machine language, multipipeline processor, pipeline bubble, pipelined application, pipelined architecture, pipeline depth, pipeline diagram, pipeline error, pipeline processing, pipeline processor, pipeline scheduling, pipeline stall, stage, superpipelined, superscalar architecture, unbalanced pipeline
2) конвейеризировать, применять конвейерVector processors pipeline and parallelize the operations on the individual elements of a vector. — Векторные процессоры производят распараллеливание и конвейеризацию операций над индивидуальными элементами вектора см. тж. pipelining
3) конвейерныйАнгло-русский толковый словарь терминов и сокращений по ВТ, Интернету и программированию. > pipeline
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